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A Phase Locked Loop Project

NXP is hosting a design competition called The Big Idea. I’ve decided to enter into this competition to go through the process of building a digital phase locked loop. I’m not going to have it be really fast; I will be happy if it works. Since I have never directly built a phase locked loop this should be a bit of a learning experience. The parts of the pll that I will be designing are the phase-frequency detector, the charge-pump, the low pass filter, the voltage controlled oscillator and the frequency divider. I’ll be documenting these sections in this blog post.

Frequency Phase Detector:

Day 2: the Phase-Frequency Detector
I’ve done a logic schematic for the phase-frequency detector for my phase lock loop. This is the part in the phase lock loop that determines what frequency the voltage controlled oscillator is set at. The schematic is an optimized version of two D-Flip Flops and some other logic. If I had the NXP part in the MultiSIM Blue library I would be able to use a single part number for each one of these logic gates.
Frequency Divider
Day 3: The Frequency Divider
One of the blocks in the phase locked loop is the frequency divider. I’ve designed a divide by 2 frequency divider out of a D-flip flop with feedback. I could use the 74AUP2G57GM in this design if it existed in the MultiSIM Blue library. However it does not. I’ve asked when they plan to have this part available and I haven’t received a reply. I’ll post the theory on my own personal blog when I’m done.
I have all the hardware I need to complete this project. I’ll be uploading a few pictures and videos in the next few days of this working. I’ve decided to close the loop with the Arduino Uno. The Arduino will receive the output of the phase-frequency detector and change the input. I needed to do this for a few reasons. The time required to assemble and debug the entire phase-locked loop would have taken longer than I would of had. Second the Arduino adds a really interesting component to this project. Since the phase-frequency detector is a very robust you can do things like lock two XBees together and double your sensor bandwidth for 3D imaging.  Or you can use it to drive two wheels forward and keep them moving at the same speed with two electric motors.
Also the demo kit that NXP sent is awesome for a lot of reasons. It allows easy prototyping of typically difficult to work with surface mount components. The kit shows how small the SMT components are. The additional resistors and capacitors for proper functionality are also included in the dev kit.  I hope NXP would consider selling it would be great to use in electrical designs that would eventually be miniaturized.
First let’s take a look at a single demo board. There are a few observations about this board I’ll make before I move onto the design.
Figure 1: Single Demo Board (Back)
As you can see in this demo board there are some added resistors and capacitors. This will help to limit the current through the device. In my original schematic I neglected these but it is clear they are needed. Second I wanted to point out the dime to the left of the board in Figure 1. If you compare Franklin D. Roosevelt’s ear to the size of the 74AUP2G57GM his ear is slightly larger! This is a very small chip; ideal for the Internet of Things and wearables.
So I was sent 5 of these boards. I can imagine they are ESD sensitive. I found some ESD Foam and used that to lay out all the boards. The boards for the phase frequency detector are shown below as well as their alignment as it shows in the schematic.
Figure 2a: The initial layout of the boards.
Figure 2b:  The schematic we are wiring to.
The next step to wire these boards as they are represented in the schematic. This was a multi-day process. I went through one board at a time and wired them per the schematic. Some of this progress is shown in Figure 3 below.
Figure 3: Some initial boards wired completed. Wiring and soldering and wiring and soldering…
So after spending time wiring and soldering and then soldering and wiring even more the entire phase frequency detector is assembled and ready to detect some frequency and phase differences! The entire device is shown below in figure 4.
Figure 4: the entire phase frequency detector
This concludes my post on assembling the phase frequency detector. In the next post we’ll plug it in and turn it on, look at some code and watch some flashing LEDs.

I will update this blog post and my blog at the big idea as I make progress.

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This idea fully exploits the configurable logic aspect of the 74aup2g57gm. This idea work similarly to AES encryption. Each configurable logic device would be act as a tumbler preceding the logic device before it. The opens and shorts would determine the resulting logic which would result in an unique code for that message. To further encrypt a GPS Time sync could be added to allow for a more obscure message. To decrypt the device would simply need to be inverted…so a message could be uniquely encoded using a basic ASCII binary representation. The hardware device would be the key for the message. so something like this could be realized. There’s probably a patent lurking somewhere within this one…. 🙂
USB -> NXP Encryption -> Computer